The present invention relates generally to metal insulator semiconductor (MIS) transistors (also known as metal-oxide-semiconductor (MIS)), and specifically to static random access memory (SRAM) cells employing MIS transistors in bistable flip-flop circuits to implement basic SRAM memory cells.
FIG. 1 illustrates a common prior art flip-flop circuit 10 constructed of a plurality of MIS transistors 12, 14, 16, 18, 20, and 22. Transistors 12 and 16 form a pull-up/pull-down pair cross-connected with another pair, transistors 14 and 18. The cross-connection makes circuit 10 bistable. Such a configuration is called a flip-flop. Transistors 20 and 22 are enabled by word line (WL). When WL is high, bit line (BL) and bit line not (/BL, [the "/" signifies inversion]) are coupled through respectively by transistors 20 and 22. If a signal point 24 is low, a signal point 26 will be high, and vice versa. Similarly if BL is high, then /BL will be low, and vice versa. If BL matches the state of point 24 when WL goes high, circuit 10 will not flip-flop. But if BL is the opposite of the state of point 24 when WL goes high, circuit 10 will flip-flop. (The same is true for /BL and point 26.) Circuit 10 is used as the basic memory cell in static random access memories (SRAMs). Note, however, that the body terminal of all the N channel type MIS transistors (16, 18, 20, and 22) are connected to V.sub.ss (ground).
FIGS. 2 and 3 illustrate the process and fabrication used in the prior art to construct circuit 10. For the sake of clarity, only one cross-section through transistors 12, 16, and 20 is discussed. Transistors 14, 18, and 22 are similarly fabricated, except to the extent that the interconnect of the schematic of FIG. 1 must be satisfied. A P-type substrate 30 has a group of N.sup.+ regions 32, 34, and 36 that form various parts of transistors 16, 18, and 20. A gate insulating layer 38 insulates the gate of transistor 16 from a first layer of N.sup.+ polycrystalline silicon layer 40 acting as a gate electrode. A gate insulating layer 42 insulates the gate of transistor 20 from a second layer of N.sup.+ polycrystalline silicon layer 44 acting as a gate electrode. The body, or substrate for both transistors 16 and 20 are, of course, common to both and connected to Vss. A gate insulating layer 46 insulates the gate of transistor 12. Layer 40 also serves as a gate electrode for transistor 12. The source and drain of transistor 12 are formed by a third layer of P.sup.+ polycrystalline silicon film 58 and a P.sup.+ polycrystalline silicon film 54, respectively, with a N.sup.- polycrystalline silicon film 52 acting as the channel. An insulating layer 48 insulates an aluminum interconnect layer 50. The source and drain of transistor 16 are formed by regions 32 and 34, respectively, with the substrate 30 acting as the channel. The source or drain and drain or source of transistor 20 are formed by regions 34 and 36, respectively, with the substrate 30 acting as the channel. (Note that the channels of transistors 16 and 20 are the same substrate 30.) Transistor 20 consumes chip real estate, versus transistor 12, which does not, because it is fabricated above transistor 16 and each has a common gate electrode. The V.sub.ss interconnects are made by a second layer of N.sup.+ polycrystalline silicon layer 56 and V.sub.dd interconnects are made by a third layer of P.sup.+ polycrystalline silicon layer 54.
A principal concern in fabricating circuit 10 is to keep its geometries small so that very dense memories can be fabricated on a single chip. But the small geometries mean reduced MIS transistor channel dimensions, and that reduces the transistors' beta (gain). Reduced betas will lead to instability and poor bistable performance.